An exemplary embodiment relates to a method of forming patterns of a semiconductor device and, more particularly, to a method of forming the patterns of a semiconductor device to improve the uniformity of a gap between patterns with different widths when forming the patterns in the same layer.
Patterns of a semiconductor device can have a variety of sizes. A NAND flash memory device is described as an example. A plurality of strings is formed in a memory cell array region of the NAND flash memory device. Each of the strings includes a source select transistor, a drain select transistor, and a plurality of memory cells coupled in series between the source select transistor and the drain select transistor. The gate of the source select transistor is coupled to the source select line, the gate of the drain select transistor is coupled to the drain select line, and the gates of the memory cells are coupled to word lines. Furthermore, each of the drain select line and the source select line can be wider than the word line. In particular, the word line can have a fine line width that is narrower than the exposure resolution limit, due to the degree of integration of such devices.
As described above, in order to form patterns each having a fine line width narrower than the exposure resolution limit, “Spacer Patterning Technology” (SPT) using spacers has been proposed. The SPT method includes processes of forming first auxiliary patterns for providing prominence and depression shapes so that spacers can be formed, depositing a spacer layer on the surface of the entire structure including the first auxiliary patterns, forming the spacers on the sidewalls of the first auxiliary patterns by etching the spacer layer using an etch method, such as etch-back, so that the spacer layer remains on the sidewalls of the first auxiliary patterns, removing the first auxiliary patterns, and etching an underlying layer using the remaining spacers as an etch mask. In accordance with the SPT method using spacers, patterns having a fine line width can be formed by controlling the thickness of the spacer layer. However, to form patterns each having a line width wider than that of the spacer, a process of forming second auxiliary patterns each having a line width wider than that of the spacer must be further performed after forming the first auxiliary patterns. The second auxiliary patterns, together with the spacer, function as an etch mask in a process of etching the underlying layer, and they are used to form patterns each having a line width wider than the spacer.
FIG. 1 is a diagram showing an alignment relationship between spacers and auxiliary patterns used to form patterns with different line widths.
Referring to FIG. 1, as described above, spacers 53, each defining the width of each of fine patterns narrower than the exposure resolution limit, are formed on sidewalls of first auxiliary patterns 51. A gap D1 between the spacers 53 is defined by the first auxiliary patterns 51. A second auxiliary pattern 55 is formed over a region in which patterns, each having a width wider than a width defined by the spacer 53, will be formed. Here, a gap D2 between a pattern defined by the second auxiliary pattern 55 and the pattern defined by the spacer 53 is determined according to the alignment of the second auxiliary patterns 55. In general, the gap D2 between the finer pattern and the pattern that is wider than the exposure resolution is wider than the gap D1 between the fine patterns defined by the spacers because of the alignment margin of the second auxiliary patterns 55. In this case, in an etch process of forming the patterns of a semiconductor device with different widths, a loading effect in which there is a difference in the degree of etching according to a difference in the density of patterns occurs, which can lead to damage to some regions of the semiconductor device. Problems occurring because of the loading effect are described in more detail below with reference to FIG. 2.
FIG. 2 is a cross-sectional view showing part of a NAND flash memory device formed using a conventional method of forming patterns of a semiconductor device.
Referring to FIG. 2, a gate pattern, including word lines WL and a select line DSL/SSL, is patterned using hard mask patterns 21 as an etch mask. The select line DSL/SSL can include a drain select line DSL or a source select line SSL.
A hard mask pattern 21 for patterning the word line WL can have a line width defined by the above-described spacer and have a line width finer than the exposure resolution. Further, a hard mask pattern 21 for patterning the select line DSL/SSL can have its line width defined by the second auxiliary pattern and have a wider line width than that of the hard mask pattern 21 for patterning the word lines WL. However, a second gap D2 between the select line DSL/SSL and a neighboring word line WL can be wider than a first gap D1 between neighboring word lines WL according to the alignment of the second auxiliary patterns. Thus, in the etch process of forming the gate pattern, layers exposed between the select line DSL/SSL and the neighboring word line WL can be etched faster than layers exposed between the word lines WL, because of a loading effect.
In general, the patterning process of forming the gate pattern is performed after stacking an isolation layer (not shown), a dielectric layer 17, and a second conductive layer 19 over the first conductive layer 15, separated from each other with the isolation layer interposed therebetween, and forming the hard mask pattern 21 over the second conductive layer 19. Before forming the dielectric layer 17, the first conductive layer 15 formed on a gate insulating layer 13 over a semiconductor substrate 11 can be separated with the isolation region interposed therebetween. The above process can be performed by stacking the gate insulating layer 13 and the first conductive layer 15 over the semiconductor substrate 11, forming an isolation mask pattern on the first conductive layer 15, forming trenches (not shown) by etching the first conductive layer 15, the gate insulating layer 13, and the isolation regions of the semiconductor substrate 11 using the isolation mask pattern as an etch mask, and then filling the trenches with the isolation layer. The height of the isolation layer preferably is lower than a top surface of the first conductive layer 15 to increase the area in which the first conductive layer 15 and the second conductive layer 19 face each other and increase the coupling ratio of the gate patterns and preferably higher than a top surface of the gate insulating layer 13 to protect the gate insulating layer 13. Consequently, the dielectric layer 17 is formed on not only the top surfaces of the isolation layer and the first conductive layer 15, but also on the exposed sidewalls of the first conductive layer 15 because of a difference in the height between the first conductive layer 15 and the isolation layer. The thickness of the dielectric layer 17 preferably is controlled so that it does not fill the space between the first conductive layers 15. Meanwhile, in the region in which the select line DSL/SSL will be formed, a contact hole through which the first conductive layer 15 is exposed is formed in the dielectric layer 17. The second conductive layer 19 is formed over the dielectric layer 17 having the contact hole formed therein.
The first conductive layer 15, the dielectric layer 17, and the second conductive layer 19 formed by the above process are etched by an etch process using the hard mask pattern 21 as an etch mask. Here, the second conductive layer 19, the dielectric layer 17, and the first conductive layer 15 are removed in the portion not blocked by the hard mask pattern 21. The second conductive layer 19, the dielectric layer 17, and the first conductive layer 15 can be etched faster in the portion opened in the second width D2, having a relatively wide width with respect to the first width D1, than in the portion opened in the first width D1. Consequently, the gate insulating layer 13 that must remain intact under the second conductive layer 19 can be damaged. To prevent such damage to the gate insulating layer 13, if the thickness of an etch target is reduced when etching the dielectric layer 17, the dielectric layer 17 can remain on the sidewalls of the first conductive layer 15, which can cause a bridge between neighboring strings and the loss of charges. Furthermore, the isolation layer is irregularly lost because of a loading effect, leading to cycling deterioration.